AT91SAM9XE512-QU【PDF 12/159 页】MCU ARM9 512K FLASH 208-PQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1904

8页 9页 10页 11页 [12页]13页 14页 15页 16页

2003 Microchip Technology Inc.

Preliminary

DS40300C-page 107

PIC16F62X

15.0 INSTRUCTION SET SUMMARY

Each PIC16F62X instruction is a 14-bit word divided

into an OPCODE which specifies the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16F62X instruction

set summary in Table 15-2 lists byte-oriented, bit-

oriented, and literal and control operations. Table 15-1

shows the opcode field descriptions.

For byte-oriented instructions, 'f' represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The destination designator specifies where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

file in which the bit is located.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 15-1:

OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basic categories:

Byte-oriented operations

Bit-oriented operations

Literal and control operations

All

instructions

are

executed

within

one

single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP

. One instruction cycle consists of four oscillator

periods. Thus, for an oscillator frequency of 4 MHz, the

normal instruction execution time is 1

s. If a

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2

Table 15-2 lists the instructions recognized by the

MPASM assembler.

Figure 15-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 15-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Field

Description

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

label

Label name

TOS

Top of Stack

Program Counter

PCLA

Program Counter High Latch

GIE

Global Interrupt Enable bit

WDT

Watchdog Timer/Counter

Timeout bit

Power-down bit

dest

Destination either the W register or the specified regis-

ter file location

[ ]

Options

( )

Contents

→

Assigned to

< >

∈

In the set of

italics

User defined term (font is courier)

Note 1: Any unused opcode is reserved. Use of

any reserved opcode may cause unex-

pected operation.

2: To maintain upward compatibility with

future PICmicro products, do not use the

OPTION

and TRIS instructions.

Byte-oriented file register operations

d = 0 for destination W

OPCODE

f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

OPCODE

b (BIT #)

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

OPCODE

k (literal)

k = 8-bit immediate value

OPCODE

k (literal)

k = 11-bit immediate value

General

CALL

and GOTO instructions only

10 9

8 7

11 10

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式